The workshop is a whole day informative program providing an overall picture of current trends and advancements in hardware security. Security and trust are paramount considerations while designing embedded systems. Majority of the embedded systems are designed using both System-on-Chip (SoC) components and software applications. While significant efforts have been made on software security for multiple decades, hardware security has got its due attention for the last few years. The objective of the workshop is to generate awareness about design aspects for hardware security among system designers, researchers, and students through interactive sessions. The whole day program will cover a wide variety of solutions related to design-for-security. The workshop would provide a broad picture of challenges and solution in the hardware security field such as security and trust verification, designing SoCs using third party IPs, trojans in SoCs, side-channel-analysis, safety and security implementations in embedded memories, security and testing etc. There will be two sessions by distinguished academicians and two sessions by eminent industry personnel.
Special Attraction: There will be a poster competition, and best posters will get recognition along with cash prize.
Audience: The workshop is targeted towards professionals from industries, faculty members, research scholars, and UG, PG students who are interested in learning about Hardware Security.
Note: Each successful participant will receive a certificate from IIIT-Delhi.
Sponsor: Scheme for Promotion of Academic and Research Collaboration (SPARC), MHRD, Government of India.
Organized by: Department of Electronics and Communication Engineering, Indraprastha Institute of Information Technology Delhi (IIIT Delhi).
Talk-1: Prof. Prabhat Mishra, Director, Embedded Systems Lab, Dept. of CISE, University of Florida, USA
Title - Securing Hardware for Designing Trustworthy Systems
Talk-2: Dr. Pramod Subramanyan, Assistant Professor, Dept. of CSE, IIT Kanpur, India
Title - End-to-end Verification of System-level Security Properties in SoC Designs
Talk-3: Dr. Ashish Kumar, Group Manager, STMicroelectronics, India
Title - Circuits and Architecture for Safety-Critical Embedded Memories
Talk-4: Mr. Vineet Dwivedi, Scientist G, SAG, DRDO, India
Title - Hardware Security and Testing
The registration fee details are given below. Fee can be paid through the IIITD Payment Portal. Please make the fee payment first and enter the "Transaction ID" of payment while filling the registration form attached below.
Note: Last date of registration is extended till July 20, 2019
Limited accommodation on payment basis is available for the participants (hostel accommodation for students and research scholars and guest house accommodation for faculties and industry persons) on first come first serve basis. For any queries, please email Sanjna Khosla (email@example.com)
A poster competition on topics related to Hardware Security is open for everyone. There are limited entries for poster competition. Submit the abstract of your poster by the following date. Selected posters will be notified to the authors via email, and would be presented by the authors during the workshop.
Last date of submission of Poster Abstract: July 20, 2019
Workshop CoordinatorFacility Coordinator
Dr. Sujay DebMrs. Sanjna Khosla
Associate Professor and HeadDepartment of ECE, IIIT Delhi
Department of ECE, IIIT DelhiEmail: firstname.lastname@example.org
Mr. Sidhartha Sankar Rout (email@example.com)
Miss. Mitali Sinha (firstname.lastname@example.org)
Mrs. Diksha Ruhela (email@example.com)
PhD Scholars, AMS Lab, Department of ECE, IIIT Delhi