Abstract:
Static Random Access Memories (SRAMs) are widely known for immediate implementation of high performance caches and also in system on chip (SoC) products. An SRAM array is composed of millions of identical SRAM bitcells, where each bitcell holds one bit of information. A 6-transistor SRAM bitcell is usually the first choice for implementation of an SRAM array. In nano-regime, 6T SRAM bitcell with minimum feature sized devices limit its viability of successful realization because of susceptibility to process variation and parametric failures. Moreover, in energy constraint and reliable applications, reduced supply or sub-threshold operation further exacerbate this problem. Therefore, recently several SRAM bitcell designs have been proposed for the target low power energy constraint applications, compatible with sub-threshold logic operations. In these designs most of the bitcells employ extra number of transistors or upsized devices to provide sub-threshold operation compatibility and robustness to the process variation.

CMOS technology scaling induced side effects such as process variation in the SRAM bitcells will be the focus of this talk. A comprehensive study of the existing SRAM designs and proposed SRAM designs will be presented. Also how the emerging devices such as Si-Tunnel FETs can be modeled for circuit level simulations. I will show how a behavioral model for TFET devices accurately captures the device physics and later it is used for SRAM bitcell simulations and demonstration of its successful realization.

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